Electronic circuitry, such as integrated circuits (ICs), is becoming increasingly complex. For example, an integrated circuit is typically assuming more functionality while executing the associated functionality at greater speeds. In order to support the functionality, which necessitates control of circuitry external to the integrated circuit (often referred as a “chip”), more input/output (IO) pins are needed to interconnect with the external circuitry. When testing a chip, the operation of a section of the chip that is associated with an IO pin typically requires observability of the IO pin. More complex chips may require more IO pins, which may require observability for verifying the operation of the chip. Apparatuses for testing chips typically are expensive, and adding additional testing channels (a testing channel being associated with an IO pin) further increases the cost of these apparatuses. A manufacturer of the chip would want to invest in testing apparatus that adequately tests the chip at the lowest amount of investment. Thus, the manufacturer would desire to adequately test a chip only with the necessary number of available testing channels in order to avert an additional investment.
FIG. 1 illustrates test logic 100 for testing electronic circuitry with the number of available input/output (IO) channels in accordance with prior art. Test logic 100 comprises a Field-Programmable Gate Array (FPGA) module 103 and a trace circuit 101.  FPGA module 103 is typically utilized to emulate (prototype) an integrated circuit design before committing the design to hardwired chips. Trace circuit 101 supports the emulation of the prototyped circuit.
Input ports IP1 105–IP6 115 provide digital stimulation (activity) of trace circuit 101, and output ports (OP1 167–OP6 177) allow access to the output from the trace circuit.
In the example shown in FIG. 1, only two tester input/output (IO) channels 151 and 153 are shown, although test logic typically supports larger numbers of tester IO channels (typically, on the order of a few hundred). Tester IO channels 151 and 153 connect to output port 1 (OP1) 167 and output port 2 (OP2) 167, respectively, as shown in FIG. 1. However, the number of available tester IO channels is typically limited because of architectural and budgetary constraints. In the example shown in FIG. 1, trace circuit 101 has more output ports than can be accommodated by the available number of tester IO channels (i.e., OP3 171, OP4 173, OP5 175, and OP6 177 are not accommodated by tester IO channels in the illustrated example). With the prior art, when there are not enough tester IO channels to cover all the output ports (corresponding to output signals), the user typically masks the output ports (where the masked output ports are not connected to any tester IO channels) that are not deemed as important as other output ports. Because test logic 100 does not have more available tester IO channels, output ports OP3 171–OP6 177 are not observable, and thus the associated circuitry of trace circuitry 101 may not be verified for proper operation. In other words, an undetectable fault in trace circuit 101 may exist.
Thus, it would be an advancement in the field of testing electronic circuitry to provide apparatuses and methods that reduce the number of required testing channels while still adequately testing the electronic circuitry. It also would be an advancement in the field of testing electronic circuitry to allow more complete visibility of an electric circuit under test using an existing number of testing channels.